1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device such as an E.sup.2 PROM having an error detecting and correcting function.
2. Description of the Relates Art
FIG. 1 is a block diagram showing the construction of an E.sup.2 PROM of a conventional type which has an error detecting and correcting circuit. The E.sup.2 PROM is included as a memory section in a microcomputer. It is assumed that a method of detecting and correcting an error employs an extended Hamming code which enables single error correction and double error detection. As shown in FIG. 1, a memory means is constituted by an E.sup.2 PROM memory cell array 10 equipped with a column latch 11 and a sense amplifier 12. A check bit generating circuit 30 is disposed between the column latch 11 and a data bus 20. (The check bit constitutes an error checking and correcting code which is hereinafter referred to as an ECC code). The sense amplifier 12 serves to read data from the memory cell array 10. The illustrated circuit of the conventional type further includes an error detecting and correcting system comprising a syndrome generating circuit 42, a syndrome decoder 41, and a bit correcting circuit 40 for detecting and correcting an error in data read from the memory cell array 10, and a multiplexer 50 for selectively outputting a syndrome 42s or corrected data 40d. In such a construction, write data 20d is supplied from a CPU (not shown) through the data bus 20 to both the column latch 11 and the ECC code generating circuit 30. The ECC code generating circuit 30 generates an ECC code 30e from the write data 20d on the basis of a generator matrix and outputs the ECC code 30e to the column latch 11. Accordingly, a systematic code composed of the write data 20d and the ECC code 30e added thereto is supplied to the column latch 11. Thereafter, the systematic code is held in the column latch 11 for a write time and thus predetermined amounts of data 20d and 30e are collectively written into the memory cell array 10.
Writing to such an E.sup.2 PROM is commonly carried out in the following manner. When a predetermined time period has elapsed after write data has been written into a column latch, the data held in the column latch is automatically written into memory cells during a write time of approximately several microseconds (us). For the sake of discrimination, the writing to the column latch is called external writing, and the writing to the memory cell is called internal writing. In the case of an E.sup.2 PROM having a page rewrite mode, a sequence of data can be written into the column latch during external writing and, when the interval of data writing exceeds a predetermined time period, the transition from the external writing into internal writing is automatically effected. Thus, the data written in the column latch is collectively written into memory cells.
During reading, readout data 12d and a readout ECC code 12e are read from the memory cell array 10 and are then output to the syndrome generating circuit 42. In accordance with a check matrix, the syndrome generating circuit 42 calculates a syndrome from the readout data 12d and the readout ECC code 12d. The decoder 41 decodes the syndrome 42s and selects a bit position at which an error exists. However, in a case where there is no error, where errors exist in many bits, or where an error exists in the check bit, none of the bits is selected. The bit correcting circuit 40 inverts the bit in the position selected by the decoder 41, and outputs the corrected data 40d to the multiplexer 50. Then, the CPU reads the corrected data 40d into the data bus 20 through the multiplexer 50, thereby effecting reading. Thus, it is possible to correct an error due to the malfunction or the like of a memory cell in the E.sup.2 PROM memory cell array 10 and read out corrected data.
Japanese Published Patent Applications 61-192099 and 62-120699 disclose means for outputting the readout ECC code 12e to the data bus 20. Further it has been also published to provide an arrangement having a structure which allows the syndrome 42s to be read out. Since the aforesaid code 42s which is ordinarily called a syndrome is described in, for example, Japanese Patent Publication No. 62-32823, the detailed description is omitted.
The conventional type of E.sup.2 PROM having an error detecting and correcting circuit is constructed in the above described manner, and the ECC code 30e generated by the ECC generating circuit 30 is necessarily read into the E.sup.2 PROM memory cell array 10 (that is, internal writing is executed.) For this reason, it is impossible to independently check a single function of the ECC code generating circuit 30, so that the overall E.sup.2 PROM (the ECC code generating circuit 30, the syndrome generating circuit 42, the decoder 41, the bit correcting circuit 40, and the E.sup.2 PROM memory cell array 10) must be checked by verifying both the write data 20d and the corrected data 40d, or by reading out the ECC code from the memory cells, or by reading out the syndrome. In addition, this method requires that write data serving as numerous test patterns be prepared and, furthermore, the method necessarily needs internal writing to the E.sup.2 PROM memory cell array. Accordingly, there is a problem in that checking requires a long time period and the efficiency of checking is inferior.